1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit (IC) device, and more particularly to a method and apparatus for the manufacture of a semiconductor IC device having discontinuous insulating layer regions for protecting the ICs from damage due to a dicing saw blade.
2. Description of the Related Arts
In general, many IC devices or chips are formed on a single semiconductor wafer during a batch processing method, which provides great economic benefit and increases productivity. Individual IC chips, called "die", are separated from the wafer during a wafer sawing or dicing step. Subsequent assembly processes are then performed on the individual chips.
FIG. 1 illustrates a conventional wafer sawing process step. A wafer 4, having a number of IC devices 6 formed thereon, is mounted to a wafer ring 2. An adhesive tape (not shown) is attached to the inactive back surface of the wafer 4. The adhesive tape supports the separated chips during subsequent process steps, e.g., a die attaching step. The wafer ring 2 is mounted to a wafer sawing machine and the wafer 4 is scribed along scribe lines or scribe regions 8 (dashed lines in FIG. 1) by a saw blade 10, and thereafter separated along such lines to divide the wafer into individual chips.
The wafer 4 is first scribed along the horizontal scribe lines, and then scribed along the vertical scribe lines. During scribing, the saw blade 10 has a revolution speed of about 30,000 to 60,000 rpm. The thickness of the saw blade 10 is about ten times greater than the thickness of the pattern layers on the IC devices. The wafer 4 can be scribed with a diamond-pointed scribing tool or cut by a laser or saw. During scribing, the wafer 4 is partially cut and therefore is not immediately separated into its individual pieces, rather it must be broken after scribing has occurred.
FIG. 2 is a partial sectional view of a semiconductor wafer depicting some of the problems that occur during the conventional wafer sawing step. The wafer 4 is scribed along the scribe line 8 by the saw blade 10 which is rotating at a high speed. In the mean time, it is common to form an insulating layer 12 between the neighboring IC devices 6. The insulating layer 12 may be a silicon dioxide (SiO.sub.2) layer, or an interlayer dielectric for the IC devices having multiple metallization layers. On the insulating layer 12, so-called TEG (Test Element Group) devices may be formed. The TEG devices are used to test the electrical characteristics of IC devices under development and confirm the stability of the existing fabrication processes of the IC devices being developed. Of course, the TEG regions can be removed before the wafer sawing step, since the test results have already been stored.
When the saw blade 10 passes along scribe lines 8 to scribe the wafer 4, the stress due to the rotating saw blade 10 is directly transferred to the fixed wafer 4. The degree of stress on the wafer 4 depends on several factors including the thickness and the revolution speed of the saw blade, scribing depth, and crystal orientation of the wafer. The strongest stress will be observed along arrow lines a' declined by about 45 degrees to the wafer surface as shown in FIG. 2. Pattern layers forming the IC devices 6 are spaced at a sufficient distance from the strongest stress position, and therefore the impact of the rotating saw blade 10 on the pattern layers is somewhat weakened. However, the rotating saw blade 10 causes the insulating layer 12 formed on the scribe line 8 to peel off from the wafer surface. This peeling off of the insulating layer 12 does cause some defects to edge portions of the IC devices 6. These defects to the edge pattern layers may eventually cause failures in the IC devices during subsequent assembly processes.
U.S. Pat. No. 5,430,325, describes a semiconductor chip having dummy patterns of a linear shape on an insulating film, as shown in FIG. 3, in an attempt to prevent peeling of the insulating layer.
Referring to FIG. 3, the disclosed IC device 6 is a light emitting diode chip (LED). A recognition mark 18 is formed on an edge of the chip for recognizing the position of the separated IC chip when the die bonding or wire bonding steps are automatically performed. The recognition mark 18 is formed through impurity diffusion of the same type as the radiating area of the LED chip and is positioned within a recognition area 20.
If the wafer is sawed along the scribe line 14 by the above-described mechanical sawing method, the insulating layer 12 begins to is peel off. If the peeling from the dicing edge 15 reaches the recognition area 20, recognition errors may occur during the steps of die bonding or wire bonding. Therefore, dummy patterns 16 are formed between the recognition area 20 and the scribe line 14 in order to prevent the peeling of the insulating layer from advancing to the recognition area 20. The dummy patterns 16 are aluminum layers which are formed on the insulating layer 12 by vapor deposition of aluminum.
The conventional dummy patterns 16 apparently prevent some damage to a particular area of the chip, e.g., the recognition area 20 caused by the peeling of the insulating layer 12. However, areas of the chip that are not protected by the dummy patterns 16 are still subject to the full effects of the saw blade 10.
Although the conventional dummy patterns, comprising an aluminum metallization layer coated on the insulating layer, somewhat prevent the peeling of the insulating layer, they do have some drawbacks. First, in order to form the aluminum layer with a sufficient thickness to protect the pattern layer of the IC devices, it is necessary to perform the chemical vapor deposition (CVD) process for an extended period. Furthermore, the aluminum metallization layer can easily corrode during subsequent assembly processes, thereby causing IC device failures.
The size of the separated IC chips obviously influence the total dimensions of the packaged devices. If the scribing position of the saw blade is close to the IC device, the mounting density of the separated IC device increases by the reduced dimension of the separated IC device. Further, if the scribing area is reduced, the number of the separated IC devices from a single wafer increases, which results in productivity improvements. However, the closer the scribing position of the saw blade is to the IC device, the greater the impact of the saw blade on the IC patterns. Therefore, it is necessary to reduce the negative impact of the saw blade while maintaining close proximity of the scribe lines to the IC devices.
If the impact of the saw blade is reduced and the scribing position of the saw blade is closer to the IC device, especially for a package device employing TAB (Tape Automated Bonding) technology, many advantages can be realized. For example, during an inner lead bonding (ILB) process in which metal bumps formed on electrode pads and individual chips are bonded to leads of TAB tape, sagging or sinking of the leads can occur. The sagging lead may cause contact between the leads and edges of the chip thereby causing electrical problems.